ppt on CMOS SCALING LIMITS AND RELIABILITY ISSUES IN VLSI DESIGNED ELECTRONIC CHIPS .pdf download

Abstract

Over the last two decades, CMOS scaling has been the driver for
Electronics industry. During the last few years, the pace of scaling has been
accelerating, and we are approaching some fundamental limits of the CMOS
technology. In this paper, some of the key challenges of the CMOS scaling, as we
approach sub 100 nm regimes, are reviewed in terms of physical and fabricating
limits. CMOS technology is facing many critical challenges to continue its scaling
trend. This affects not only the fabrication technologies but also various VLSI
design rules that are to be implemented while designing a chip. We discussed about
various fabrication as well as design issues following Moore’s law and what
happens when it reaches its limit as continuous scaling of VLSI devices take place.
Apart from that, various VLSI chip reliability issues both at design and device
phase and various methods proposed by researchers were also discussed. We see
VLSI as a chip fabrication methodology as well as design methodology in this
paper.

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